If interested on how Chimera works, here is its whitepaper.
According to this paper, Chimera architecture essentially pipelines the stages where ISP/CPU/GPU modifies data obtained through the sensor. This reduces latency between consecutive reads from the CMOS sensor.
However, there might be work around for the HDR problem Chimera is trying to solve using other SoC's. One way is to buffer as many pictures as possible before processing them in batch. This should reduce latency between pictures. Of course, this would require a big buffer...
This brings me a question: Does the Chimera architecture use a large (at least larger than normal) cache that is shared between ISP/CPU/GPU?
If interested on how Chimera works, here is its whitepaper.
According to this paper, Chimera architecture essentially pipelines the stages where ISP/CPU/GPU modifies data obtained through the sensor. This reduces latency between consecutive reads from the CMOS sensor. However, there might be work around for the HDR problem Chimera is trying to solve using other SoC's. One way is to buffer as many pictures as possible before processing them in batch. This should reduce latency between pictures. Of course, this would require a big buffer...
This brings me a question: Does the Chimera architecture use a large (at least larger than normal) cache that is shared between ISP/CPU/GPU?
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